// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:09 UTC 2022
////////////////////////////////////////////////////////////////////////////// 
//
//  cr_r_reg.v
//
//  Control Register for read-only values
//
//  Original Author: Chris Jones
//  Current Owner:   Behram Minwalla
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: ameer $
//    $File: //dwh/up16/main/dev/pma/dig/rtl/cr_r_reg.v $
//    $DateTime: 2013/05/16 12:52:57 $
//    $Revision: #1 $
//
////////////////////////////////////////////////////////////////////////////// 

`include "dwc_e12mp_phy_x4_ns_cr_macros.v"

module dwc_e12mp_phy_x4_ns_cr_r_reg
  #(parameter WIDTH = 1) (

output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_rd_data,
input  wire                       cr_sel,
input  wire [WIDTH-1:0]           cr_val
);

// Read logic - using generate statement to hopefully avoid compile-time or lint warnings
//
generate
  if (WIDTH == `DWC_E12MP_X4NS_CR_DATA_LEN) begin: FULL_LEN
    assign cr_rd_data = ({`DWC_E12MP_X4NS_CR_DATA_LEN{cr_sel}} & cr_val);
  end
  else begin: PART_LEN 
    assign cr_rd_data = ({`DWC_E12MP_X4NS_CR_DATA_LEN{cr_sel}} &
                        {{`DWC_E12MP_X4NS_CR_DATA_LEN-WIDTH{1'b0}},cr_val});
  end
endgenerate

endmodule
